View S6A0072_78445.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
INTRODUCTION
S6A0072 is a dot matrix LCD driver & controller IC which is fabricated by low power CMOS technology. It is capable of displaying 1-line 16 characters or 2-line 8 characters with 5 x 8 dots format.
FUNCTIONS
Character type dot matrix LCD driver & controller * * * * * * * Easy interface with 4-bit or 8-bit MPU. Internal driver: 16 common and 40 segment signal output. Display character pattern: 5 x 8 dots format (240 kinds) Direct programming of the special character patterns by character generator RAM Mask option for programming customer character patterns Various instruction functions Automatic power on reset
FEATURES
* Internal Memory - Character Generator ROM (CGROM): 9600 bits (240 characters x 5 x 8 dot) - Character Generator RAM (CGRAM): 160 bits (4 characters x 5 x 8 dot) - Display Data RAM (DDRAM): 128 bits (16 characters x 8bits) Low power operation - Power supply voltage range: 2.7 to 5.5V (VDD) - LCD drive voltage range: 3.0 to 11.0 (VDD-V5) CMOS process Duty cycle: 1/16 Built-in oscillator Low power consumption Internal divide resistor for LCD driving voltage COG available
*
* * * * * *
1
S6A0072
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
BLOCK DIAGRAM
TEST Oscillator Power on Reset (POR) RESET EXTCLK
EXT_INT
Timing Generator
8
Instruction Register (IR)
Instruction Decoder Display Data RAM (DDRAM) 16 x 8-bit 16-bit Shift Register Common C1-C16 Driver
DB0-DB7
8 Address Counter
RS R/W
Input Buffer 8
E 8 Data Register (DR) 8 40-bit Shift Register 40-bit Segment S1-S40 Latch Driver Circuit
8
8 VDD
Character Generator RAM (CGRAM) 32 bytes
Character Generator ROM (CGROM) 9600 bits
Cursor Blink Control Circuit
V1 V2 V3 V4
VDD Parallel to Serial Converter
V5
GND(VSS)
2
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
PAD DIAGRAM
DUMMY C16 C15 C14 C13 C12 C11 C10 C9 TEST DUMMY DUMMY DUMMY DUMMY DUMMY
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40
S6A0072
Y
(0, 0)
X
C8 C7 C6 C5 C4 C3 C2 C1 DB7 DB6 DB5 DB4
EXT_INT EXTCLK DUMMY
VSS VSS VSS
VDD VDD VDD
V5 V5 V5
V3
V2
RESET
RS
R/W
E
DB3 DB2 DB1 DB0
DUMMY
S6A0072 Chip Size: 7600 x 2160 m Pad pitch: min. 125 m Chip thickness 675 m Al Pad Specifications AL pad size on Y side: 87 x 94 m AL pad size on X side: 94 x 87 m Au Bump Specifications Bump size on Y side: 77 x 84 m Bump size on X side: 84 x 77m Bump height: 18 1m
3
S6A0072
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
PAD CENTER COORDINATES
Unit: um
Pad No. Pad Name Coordinate X Y Pad No. Pad Name Coordinate X Y Pad No. Pad Name Coordinate X Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
DUMMY DUMMY EXTCLK EXT_INT VSS VSS VSS VDD VDD VDD V5 V5 V5 V3 V2 RESETB RS R/W E DB0 DB1 DB2 DB3 DUMMY DB4 DB5 DB6 DB7 C1 C2
-3642 -3032 -2632 -2232 -1832 -1707 -1582 -1182 -1057 -932 -532 -407 -282 117 517 917 1317 1717 2117 2521 2697 2871 3047 3643 3643 3643 3643 3643 3643 3643
-881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -881 -717 -591 -467 -341 -184 -60
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
C3 C4 C5 C6 C7 C8 DUMMY S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23
3643 3643 3643 3643 3643 3643 3643 2464 2329 2204 2079 1954 1829 1704 1579 1454 1329 1204 1079 954 829 704 579 454 329 204 71 -70 -205 -330
64 189 314 439 564 689 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 DUMMY C16 C15 C14 C13 C12 C11 C10 C9 TEST DUMMY DUMMY DUMMY
-455 -580 -705 -830 -955 -1080 -1205 -1330 -1455 -1580 -1705 -1830 -1955 -2080 -2205 -2330 -2463 -3642 -3643 -3643 -3643 -3643 -3643 -3643 -3643 -3643 -3643 -3643 -3643 -3643
923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 923 689 564 439 314 189 64 -60 -184 -341 -467 -592 -717
4
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
PIN DESCRIPTION
Pin VDD VSS (GND) V2, V3, V5 S1 - S40 C1 - C16 EXTCLK Output Input Input Segment output Common output External clock Input External/internal oscillator clock select Register select Input/Output Power Name Power supply & LCD bias pin Description for logical circuit (+3V, +5V) 0V (GND) Bias voltage level for LCD driving Segment signal output for LCD driving Common signal output for LCD driving When using external clock, used as clock input pin. When using internal oscillator, connect to VDD or VSS. When EXT_INT = "High", external clock is used. When "Low", internal oscillator is used. Used as register selection input. When RS = "High", Data register is selected. When RS = "Low", Instruction register is selected. Used as read/write selection input. When R/W = "High", read operation. When R/W = "Low", write operation. Used as read/write enable signal. When 8-bit bus mode, used as low order bi-directional data bus. During 4-bit bus mode open these pins. When 8-bit bus mode, used as high order bidirectional data bus. In case of 4-bit bus mode, used as both high and low order. DB7 is used for busy flag output during read instruction operation. Input Reset If it is necessary to initialize the system by hardware, force "Low", level signal to this terminal about 1.2ms. Internal oscillator test pin. Open this pin. Open LCD LCD External clock Interface Power supply
EXT_INT
Input
VDD/VSS
RS
Input
MPU
R/W
Input
Read/write
E DB0-DB3
Input Input/Output
Read/write enable Data bus 0 - 7
DB4-DB7
RESETB
TEST
Output
Test pin
5
S6A0072
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
FUNCTION DESCRIPTION
SYSTEM INTERFACE This chip consists of two kinds of interface type with MPU: 4-bit bus and 8-bit bus. 4-bit bus and 8-bit bus is selected by DL bit of function set in the instruction register. During read or write operation, two 8-bit registers are used. One is the data register (DR), the other is the instruction register (IR). The data register (DR) is used as a temporary data storage place for being written into or read from DDRAM/CGRAM, target RAM is selected by RAM address setting instruction. Each internal operation, reading from or writing into RAM, is done automatically. Thus, after MPU reads DR data, the data in the next DDRAM/CGRAM address is transferred into DR automatically. Also after MPU writes data to DR, the data in DR is transferred into DDRAM/CGRAM automatically. The Instruction register (IR) is used only to store instruction code transferred from MPU. MPU cannot read data from instruction register. The register selection depends on RS input pin setting in both 4-bit bus mode. Table 1. Various Kinds Of Operations According to RS and R/W Bits RS 0 0 1 1 R/W 0 1 0 1 Operation Instruction write operation (MPU writes Instruction code into IR) Read busy flag (DB7) and address counter (DB0 - DB6) Data write operation (MPU writes data into DR) Data read operation (MPU reads data from DR)
BUSY FLAG (BF) BF = "High" indicates that the internal operation is being processed. So during this time the next instruction cannot be accepted. BF can be read, when RS = Low and R/W = High (Read instruction Operation), through DB7 port. Before executing the next instruction, be sure that BF is not High. ADDRESS COUNTER (AC) Address Counter (AC) stores the address of DDRAM/CGRAM that are transferred from IR. After writing into (reading from) DDRAM/CGRAM data, AC is increased (decreased) by 1 automatically. When RS = "Low", and R/W = "High", AC value can be read through DB0 - DB6 ports.
6
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
DISPLAY DATA RAM (DDRAM) DDRAM stores 8bits character code in CGROM/CGRAM and its maximum number is 16 (16 Characters). DDRAM address is set by the address counter (AC) as hexadecimal number.
MSB AC6 AC5 HEX AC4 AC3 AC2 AC1 LSB AC0
HEX
The relations of DDRAM address and display position is as follows. 1) DDRAM Addressing Mode 0 (A = 0)In this addressing mode, the address range of DDRAM is 00H - 0FH.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Display Position DDRAM Address
00 01 02 03 04 05 06 07 COM1 - COM8
08 09 0A 0B 0C 0D 0E 0F COM9 - COM16
After Shift Left:
COM1 COM8
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
01 02 03 04 05 06 07 08
09 0A 0B 0C 0D 0E 0F 00
COM9 COM16
After Shift Right:
COM1 COM8
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
0F 00 01 02 03 04 05 06
07 08 09 0A 0B 0C 0D 0E
COM9 COM16
2) DDRAM Addressing Mode 1 (A = 1) In this addressing mode, the address range of DDRAM is 00H - 07H and 40H - 47H.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Display Position DDRAM Address
00 01 02 03 04 05 06 07 COM1 - COM8
40 41 42 43 44 45 46 47 COM9 - COM16
1 COM1 After Shift Left: COM8
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 COM9 COM16
01 02 03 04 05 06 07 40
41 42 43 44 45 46 47 00
1 After Shift Right: COM1 COM8
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 COM9 COM16
4F 00 01 02 03 04 05 06
07 40 41 42 43 44 45 46
7
S6A0072
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
CHARACTER GENERATOR RAM (CGRAM) CGRAM is used for user defined character pattern. The format of the character pattern is 5 x 7 dots except for the cursor position and has a maximum of 4 characters. To use the character pattern in CGRAM write the character code into DDRAM as shown in table 2. Table 2. Relationship Between Character Code (DDRAM) and Character Pattern (CGRAM)
Character Code (DDRAM data) CGRAM Address CGRAM Data D7 D6 D5 D4 D3 D2 D1 D0 A4 A3 A2 A1 A0 P7 P6 P5 P4 P3 P2 P1 P0 0 0 0 0 * * 0 0 0 0 0 0 0 x x x 0 1 1 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 1 . . 0 0 0 1 1 1 1 1 1 1 . . . . 0 0 1 0 0 1 0 0 0 1 . . 0 0 1 0 1 1 0 0 0 1 . . 0 0 1 1 0 1 0 0 0 1 0 . . 0 0 0 0 * * 1 1 . . 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 . . 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x x x 1 1 1 1 1 1 1 0 1 0 . . 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 1 1 1 0 0 0 0 0 0
Pattern Number Pattern 1
Cursor position . . Pattern 4
. . . . .
. . . . .
Cursor position
NOTE: "" don' t care.
8
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
CHARACTER GENERATOR ROM (CGROM) CGROM generates 5 x 8 character pattern from character generate code in DDRAM. CGROM has 5 x 8-dot 240 character pattern including cursor position. If the data in cursor position bit are high, the data are included to the character pattern. So, the selected positions are always "ON" regardless to cursor position. The relationship between character code and character pattern can be referred to table 5. TIMING GENERATION CIRCUIT Timing generation circuit generates clock signals for the internal operations. LCD DRIVER CIRCUIT LCD driver circuit has 16 common and 40 segment output signals for LCD driving. Data from CGRAM/CGROM is transferred to 40-bit segment shift register serially, then it is stored to 40-bit segment output latch. When each com is selected by a 16-bit common register, the segment data also outputs through segment driver from 40-bit segment output latch. CURSOR/BLINK CONTROL CIRCUIT It controls cursor/blink ON/OFF at the cursor position.
9
S6A0072
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
INSTRUCTION DESCRIPTION
OUTLINE To overcome the speed difference between the internal clock of S6A0072 and the MPU clock, the S6A0072 performs an internal operation by storing control information to IR or DR. The internal operation is determined according to the signal from MPU, composed of read/write and data bus. Instruction can be divided into four types: * * * * S6A0072 function set instructions (set display methods, set data length, etc.) Address set instructions to internal RAM Data transfer instructions with internal RAM Others.
The address of internal RAM is automatically increased or decreased by 1.
NOTE: During an internal operation, the busy flag (DB7) is high. Busy flag check must precede the next instruction. When an MPU program with busy flag (DB7) checking is made, 1/2Fosc is necessary for executing the next instruction by the falling edge of the "E" signal after the busy flag (DB7) goes to "Low".
10
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
Table 3. Instruction Table
Instruction Instruction Code RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Test mode 0 0 0 0 0 0 0 0 0 0 Device test mode (When 4-bit interface mode) No operation (When 8-bit interface mode) Write "20H" to DDRAM and set DDRAM address to "00H" from AC. Set DDRAM address to "00H" from AC and return cursor to its original position if shifted. The contents of DDRAM are not changed. Assign cursor moving direction and enable entire display shift. All display (D), cursor (C), and blinking of cursor position character on/off control bit (B). Cursor and display shift and their direction control without changing DDRAM data. Set interface data length (DL), DDRAM addressing mode (A) and COM/SEG output pattern (M0, M1). Description Execution Time (fosc = 270kHz) -
Clear display
0
0
0
0
0
0
0
0
0
1
631s
Return home
0
0
0
0
0
0
0
0
1
*
631s
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
39s
Display ON/OFF control
0
0
0
0
0
0
1
D
C
B
39s
Cursor or display shift Function set
0
0
0
0
0
1
S/C
R/L
*
*
39s
0
0
0
0
1
DL
A
*
M1
M0
39s
Set CGRAM address Set DDRAM address Read busy flag and Address DDRAM
0 0 0
0 0 1
0 1 BF
1
*
AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter.
39s 39s 0s
AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter. AC6 AC5 AC4 AC3 AC2 AC1 AC0 Whether in internal operation or not can be known by reading BF. The contents of address counter can also be
CGRAM
*
*
AC4 AC3 AC2 AC1 AC0 read
Note: "*" don't care.
11
S6A0072
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
Table 3. Instruction Table (Continued)
Instruction Instruction Code Description Execution Time (fosc = 270kHz) Write data into internal RAM (DDRAM/CGRAM). 43s
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write data to RAM DDRAM 1 0 D7 D6 D5 D4 D3 D2 D1 D0
CGRAM Read data from RAM DDRAM 1 1
* D7
* D6
* D5
D4 D4
D3 D3
D2 D2
D1 D1
D0 D0 Read data from internal RAM (DDRAM/CGRAM). 43s
CGRAM
*
*
*
D4
D3
D2
D1
D0
Note: "*" don't care. I/D = 1: Increment, S = 1: Shift enable, S/C = 1: Display shift, R/L = 1: Shift right, DL = 1: 8-bit interface, A = 0: DDRAM addressing mode 0, M0 = 0: COM/SEG output pattern A, M1 = 0: 1 line 16 characters, BF = 1: System is in operation I/D = 0: Decrement S = 0: Shift disable S/C = 0: Move cursor R/L = 0: Shift left DL = 0: 4-bit interface A = 1: DDRAM addressing mode1 M0 = 1: COM/SEG output pattern B M1 = 1: 2 line 8 characters BF = 0: System is ready
12
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
CONTENTS Test Mode RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
After setting the DL bit to 4-bit data interface mode (DL = 0), writing this code twice makes the system go to test mode. And when 8-bit interface mode (DL = 1) is set, normal function mode is returned. System is unaffected if this code is set in 8-bit interface, other than consuming some time. (37s at fosc = 270kHz) Clear Display RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Clear all the display data by writing "20H" (space code of CGROM) to all DDRAM address, and set DDRAM address to "00H" into AC (Address Counter). For this instruction, the CGROM address "20H" has to be set to space code. Shifting of the display position returns it to the original position. Namely, when display data is shifted and cursor or blinking is displayed, bring the cursor to the left edge on first line of the display. It makes entry mode to increment (I/D = 1) Return Home RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 *
Set DDRAM address to "00H" into the address counter. Shifting of the display position returns it to the original position. When cursor or blinking is displayed, bring the cursor to the left edge on first line of the display. The data in DDRAM does not change. Entry Mode Set RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 S
Set the moving direction of cursor and display. I/D: Increment/decrement of DDRAM/CGRAM address (cursor or blink) When I/D = "High", cursor/blink moves to right and DDRAM address is increased by 1. When I/D = "Low", cursor/blink moves to left and DDRAM address is decreased by 1. Shift of entire display When DDRAM read (CGRAM read/write)operation or S = "Low", entire display is not shift. If S = "High", and DDRAM write operation, entire display is shifted according to I/D value (I/D = "1": shift left, I/D = "0": shift right).
S:
13
S6A0072
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
Display ON/OFF Control RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B
Control display/cursor/blink ON/OFF 1 bit register. D: Display ON/OFF control bit When D = "High", entire display is turned on. When D = "Low", entire display is turned off, but display data is remains in DDRAM. Cursor ON/OFF control bit When C = "High", cursor is turned on. When C = "Low", cursor is disappeared in current display, but I/D register preserves its data. Cursor Blink ON/OFF control bit When B = "High", cursor blink is on, performs alternately between all high data (black pattern) and display character at the cursor position. When B = "Low", blink is off.
C:
B:
Cursor or Display Shift RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 S/C DB2 R/L DB1 * DB0 *
Without writing or reading of display data, shift right/left the cursor position or display. This instruction is used to correct or search display data. (Refer to Table 4) during 2-line mode display, cursor moves to the 2nd line after 8th digit of 1st line. Note that display shift is performed simultaneously in all the line. When displayed data is shifted repeatedly, each line is shifted individually. When display shift is performed, the contents of address counter are not changed. Table 4. Shift patterns according to S/C and R/L bits R/C 0 0 1 1 R/L 0 1 0 1 Operation Shift cursor to the left, AC is decreased by 1 Shift cursor to the right, AC is increased by 1 Shift all the display to the left, cursor moves according to the display Shift all the display to the right, cursor moves according to the display
14
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
Function Set RS 0 DL: R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL DB3 A DB2 * DB1 M1 DB0 M0
Interface data length control bit When DL = "High" 8-bit bus mode with MPU. When DL = "Low", 4-bit bus mode with MPU. Thus, DL is a signal to select 8-bit or 4-bit bus mode. In 4-bit bus mode, the 4-bit data is transferred twice. Set the display data addressing mode When A = "Low", DDRAM addressing mode 0. When A = "High", DDRAM addressing mode 1. Set COM/SEG output rotation When M0 = "Low", COM/SEG output rotation mode A. When M0 = "High", COM/SEG output rotation mode B. Set display line and character mode When M1 = "Low", 1 line 16 character display mode. When M1 = "High", 2line 8 character display mode. (refer to application information)
A:
MO:
M1:
Set CGRAM Address RS 0 R/W 0 DB7 0 DB6 1 DB5 * DB4 AC4 MSB DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0 LSB
Set CGRAM address to AC. This instruction allows the MPU to access CGRAM data for user defined character pattern. Available CGRAM Address is lower 5 bits (DB4 - DB0). Set DDRAM Address RS 0 R/W 0 DB7 1 DB6 AC6 DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0
Set DDRAM address to AC. This instruction allows the MPU to access DDRAM data. When DDRAM addressing mode 1 (A = 0), DDRAM address is from "00H" - "0FH". In DDRAM addressing mode 2 (A = 1), DDRAM address range of the 1st 8 character is "00H" - "07H", and DDRAM address range of the 2nd 8 character is "40H" - "47H".
15
S6A0072
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
Read Busy Flag & Address DDRAM RS 0 R/W 0 DB7 BF DB6 AC6 MSB DB5 AC5 DB4 AC4 DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0 LSB
CGRAM RS 0 R/W 0 DB7 BF DB6 * DB5 * DB4 AC4 MSB DB3 AC3 DB2 AC2 DB1 AC1 DB0 AC0 LSB
This instruction shows whether S6A0072 is in internal operation or not. If the resultant BF is high, The internal operation is in progress and should wait until BF to be low, which by then the next instruction can be performed. In the instruction you can read also the value of address counter. Write Data to RAM Write binary 8/5 bit data to DDRAM/CGRAM. The selection of RAM from DDRAM/CGRAM is set by the previous address set instruction (DDRAM address set, CGRAM address set). After writing operation, the address is automatically increased/decreased by 1, according to the entry mode. Read Data From RAM DDRAM RS 1 R/W 0 DB7 D7 MSB DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0 LSB
CGRAM RS 1 R/W 0 DB7 * DB6 * DB5 * DB4 D4 MSB DB3 D3 DB2 D2 DB1 D1 DB0 D0 LSB
16
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
READ BINARY 8/5 BIT FROM DDRAM/CGRAM The selection of RAM is set by the previous address set instruction. If the address set instruction of RAM is not performed before this instruction, data that was read first becomes invalid, as the direction of AC is not determined. If RAM data is read several times without RAM address set instruction before read operation, the correct RAM data can be detained from the second, but the first data would be incorrect, as there is no time margin to transfer the RAM data. In case of DDRAM reading operation, the cursor shift instruction plays the same role as DDRAM address set instruction also transfers RAM data to output data register. After read operation address counter is automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, the display shift may not be executed correctly. - In the case of RAM write operation, AC is increased/decreased by 1 like read operation (after this operation). In this time, AC indicates the next address position, but only the previous data can be read by read instruction.
17
S6A0072
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
INTERFACE WITH MPU
INTERFACE WITH 8-BIT MPU With 8-bit interfacing data length transfer is performed at a time through 8 ports, from DB0 - DB7. Example of timing sequence is shown below.
RS R/W E Internal Signal DB7
Data Internal Operation No Bus y
Busy
Busy
Data
Instruction
Busy Flag Check
Busy Flag Check
Busy Flag Check
Instruction
Figure 1. Example of 8-bit Bus Mode Timing Diagram INTERFACE WITH 4-BIT MPU When interfacing data length are 4-bit, only 4 ports, from DB4 - DB7, are used as data bus. At first higher 4-bit (in case of 8-bit bus mode, the contents of DB4-DB7) are transferred, then the lower 4-bit (in case of 8-bit bus mode, the contents of DB0-DB3) are transferred. So transfer is performed twice. Busy Flag outputs "High" after the second transfer are ended. Example of timing sequence is shown below.
RS R/W E Internal Signal DB7
D7 D3 Internal Operation No Bus y
Busy
AC3
AC3
D7
D3
Instruction
Busy Flag Check
Busy Flag Check
Instruction
Figure 2. Example of 4-bit Bus Mode Timing Diagram
18
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
APPLICATION INFORMATION
COM/SEG OUTPUT ROTATION MODE A DDRAM Address Mode 0 (A = 0)
S1
S20
S40
S21
S21
S40
S20
S1
SEG1
SEG20 SEG21
SEG40
SEG41
SEG60 SEG61
SEG80
S1 C8
S20
S21
S40 C16
S6A0072
Bottom View
C1 C9
(M0 = 0, M1 = 0)
19
S6A0072
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
DDRAM Address Mode 1 (A = 1)
S1
S20
S21
S40
SEG1
SEG20
SEG21
SEG40
SEG41
SEG60
SEG61
SEG80
S1 C8
S20 S21
S40 C16
S6A0072
Bottom View
C1 C9
(M0 = 0, M1 = 1)
20
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
COM/SEG OUTPUT ROTATION MODE B DDRAM Address Mode 0 (A = 0)
S40
S21
S1
S20
S20
S1
S21
S40
SEG1
SEG20 SEG21
SEG40
SEG41
SEG60 SEG61
SEG80
S40 C16
S21
S20
S1 C8
S6A0072
Top View
C9 C1
(M0 = 1, M1 = 0)
21
S6A0072
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
DDRAM Address Mode 1 (A = 1)
S40
S21
S20
S1
SEG1
SEG20
SEG21
SEG40
SEG41
SEG60
SEG61
SEG80
S40 C16
S21 S20
S1 C8
S6A0072
Top View
C9 C1
(M0 = 1, M1 = 1)
22
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
POWER SUPPLY FOR DRIVING LCD PANEL
VDD
S6A0072
V1 V2
R R R
V3 V4 R R
V5
R = 1.5k (Typ) 30%
23
S6A0072
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
INITIALIZING
INITIALIZE BY INTERNAL POWER-ON-RESET CIRCUIT When the power is turned on, S6A0072 is initialized automatically by power on reset circuit. During the initialization, the following instructions are executed, and BF (Busy Flag) is kept "High" (busy state) up to the end of initialization. INITIALIZE FLOW Display Clear Write "20H" to all DDRAM Set Functions DL = 1: 8-bit bus mode A = 0: DDRAM addressing mode 0 M0 = 0: COM/SEG output rotation mode A M1 = 0: 1 line 16 character display mode Control Display ON/OFF instruction D = 0: Display OFF C = 0: Cursor OFF B = 0: Blink OFF Set Entry Mode I/D = 1: Increment by 1 S = 0: No entire display shift INITIALIZE BY EXTERNAL HARDWARE RESET If the "Low" signal is forced to reset terminal over a period of 1.2 ms then system will be initialized. And BF (Busy Flag) is kept "High" (busy state) for 629 us after releasing the initializing sequence.
24
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
INITIALIZING BY INSTRUCTION 8-bit Interface Mode
Power On
Condition: fosc = 270kHz 0 4-bit interface
Wait for more than 20ms after VDD rises to 4.5V Wait for more than 30ms after VDD rises to 2.7V
DL 1 8-bit interface 0 DDRAM addressing mode 0 A 1 DDRAM addressing mode 1 0 mode A COM/SEG output rotation 1 0
COM/SEG output rotation
Function Set RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL(1) DB3 A DB2 * DB1 M1 DB0 M2
M0
M1
mode B 1-line 16 character display mode 2-line 8 character display 1 mode
Wait for more than 39 s 0 D Display ON/OFF Control RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 C B B Wait for more than 39 s 1 Blink on 1 0 Cursor on Blink off 1 0 Display on Cursor off Display off
Clear Display RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Wait for more than 631us 0 Entry Mode Set RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 0 S S 1 Initialization End Entire shift on Entire shift off I/D 1 Increment mode Decrement mode
25
S6A0072
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
4-bit Interface Mode
Power On
Condition: fosc = 270kHz 0 4-bit interface 8-bit interface
DDRAM addressing mode 0 DDRAM addressing mode 1 COM/SEG output rotation mode A COM/SEG output rotation mode B 1-line 16 character display mode 2-line 8 character display mode
Wait for more than 20ms after VDD rises to 4.5V Wait for more than 30ms after VDD rises to 2.7V
DL 1 0 A 1 0
Function Set (4-bit mode change) RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL(0) DB3 x DB2 x DB1 x DB0
M0 1 0 x M1 1
Wait for more than 39 s
Function Set (display mode set) RS 0 0 R/W 0 0 DB7 0 A DB6 0 * DB5 1 M1 DB4 0 M0 DB3 x x DB2 x x DB1 x x DB0 x x
Wait for more than 39 s 0 D Display ON/OFF Control RS 0 0 R/W 0 0 DB7 0 1 DB6 0 D DB5 0 C DB4 0 B DB3 x x DB2 x x DB1 x x DB0 C x x B 1 Wait for more than 39 s Blink on 1 0 Cursor on Blink off 1 0 Display on Cursor off Display off
Display Clear RS 0 0 R/W 0 0 DB7 0 0 DB6 0 0 DB5 0 0 DB4 0 1 DB3 x x DB2 x x DB1 x x DB0 x x
Wait for more than 631 s
Entry Mode Set I/D RS 0 0 R/W 0 0 DB7 0 0 DB6 0 1 DB5 0 I/D DB4 0 S DB3 x x DB2 x x DB1 x x DB0 x S x
0 1 0 1
Decrement mode Increment mode Entire shift off Entire shift on
Initialization End
X: Open *: Don't care
26
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
FRAME FREQUENCY 1/16 Duty Cycle
1-line selection period 1 VCC V1 COM1 V4 V5 1 Frame 1 Frame .. 2 3 4 ... 15 16 1 2 3 ... 15 16
1-line selection period = 160 clocks One Frame = 40 x 16 x 3.7s x 4 = 9.472ms (1 CLOCK = 3.7s at fosc = 270KHz) Frame frequency = 1/9.472ms = 105.6Hz
27
S6A0072
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
MAXIMUM ABSOLUTE LIMIT
MAXIMUM ABSOLUTE POWER RATINGS Characteristic Power supply voltage (1) Power supply voltage (2) Input voltage Symbol VDD VLCD VIN Value -0.3 to +7.0 -0.3 to +13 -0.3 to VDD+0.3 Unit V V V
Voltage greater than above may damage to the circuit (VDD V2 V3 V5, VLCD = VDD-V5) TEMPERATURE CHARACTERISTICS Characteristic Operating temperature Storage temperature Symbol TOPR TSTG Value -30 to +85 -55 to +125 Unit C C
28
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS TABLE 5. DC CHARACTERISTICS (VDD = 4.5 to 5.5V, Ta = -30 to +85C) Characteristic Operating voltage Supply current Input voltage (1) (except EXTCLK) Symbol VDD IDD VIH1 VIL1 Input voltage (2) (EXTCLK) VIH2 VIL2 Input voltage (3) (E pin) VIH3 VIL3 Output voltage (1) (DB0 - DB7) VOH1 VOL1 Voltage drop VdCOM VdSEG Input leakage current Low input current LCD driving voltage IIL IIN V2 V3 Divide resistor RB VDD - V5 = 5V RB = (VDD-V5)/IB IB = Divide resistor current VDD = 5V VDD - V5 VIN = 0V - VDD VIN = 0V, VDD = 5V (pull up) VDD = 5V, V5 = 0V SEG output port Condition Internal oscillation (VDD = 5.0V, fosc = 270kHz) IOH = -0.205(mA) IOL = 1.6(mA) IO = 0.1(mA) Min 4.5 0.7VDD -0.3 VDD-1.0 -0.2 0.8VDD 2.4 -1 -50 2.7 1.7 3.7 Typ 1.5 -125 3.0 2.0 7.5 Max 5.5 1.8 VDD 0.8 VDD 1.0 VDD 0.2VDD 0.4 1 1 1 -250 3.3 2.3 11.5 k V A V V V V Unit V mA V
Internal clock (internal Rf) LCD driving voltage
f IC VLCD
190 3.0
270 -
350 11.0
kHz V
29
S6A0072
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
(VDD = 2.7 to 4.5V, Ta = -30 to +85C) Characteristic Operating voltage Supply current Input voltage (1) (except EXTCLK) Symbol VDD IDD VIH1 VIL1 Input voltage (2) (EXTCLK) VIH2 VIL2 Input voltage (3) (E pin) VIH3 VIL3 Output voltage (1) (DB0 - DB7) VOH1 VOL1 Voltage drop VdCOM VdSEG Input leakage current Low input current LCD driving voltage IIL IIN V2 V3 Divide resistor RB VDD - V5 = 5V RB = (VDD-V5)/IB IB = Divide resistor current VDD = 5V VDD - V5 IOH = -0.1(mA) IOL = 0.1(mA) IO = 0.1(mA) VLCD = 5V VIN = 0V - VDD VIN = 0V, VDD = 3V (pull up) VDD = 3V, V5 = -2V SEG output port Condition Internal oscillation (VDD = 3.0V, fosc = 270kHz) Min 2.7 0.7VDD -0.3 VDD-1.0 -0.2 0.8VDD 0.75 VDD -1 -10 0.7 -0.3 3.7 Typ 0.5 -50 1.0 0 7.5 Max 4.5 1.2 VDD 0.4 VDD 0.2 VDD VDD 0.4 0.2 VDD 1 1 1 -120 1.3 0.3 11.5 k V A V V V V Unit V mA V
Internal clock (internal Rf) LCD driving voltage
f IC VLCD
190 3.0
270 -
350 11.0
kHz V
30
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
S6A0072
AC CHARACTERISTICS Table 6. AC Characteristics (VDD = 4.5 TO 5.5V, TA = -30 TO +85C) Mode Write mode (refer to Figure 3) E cycle time E rise/fall time E pulse width (high, low) R/W and RS setup time R/W and RS hold time Data setup time Data hold time Read mode (refer to Figure 4) E cycle time E rise/fall time E pulse width (high, low) R/W and RS setup time R/W and RS hold time Data output delay time Data hold time Item Symbol tc, tr, tf tw tsu1 th1 tsu2 th2 tc tr, tf tw tsu th tD tDH Min 500 230 40 10 80 10 500 230 40 10 20 Typ Max 20 20 120 ns Unit ns
Table 6. AC Characteristics (VDD = 2.7 TO 4.5V, TA = -30 TO +85C) Mode Write mode (refer to Figure 3) E cycle time E rise/fall time E pulse width (high, low) R/W and RS setup time R/W and RS hold time Data setup time Data hold time Read mode (refer to Figure 4) E cycle time E rise/fall time E Pulse width (high, low) R/W and RS setup time R/W and RS hold time Data output delay time Data hold time Item Symbol tc, tr, tf tw tsu1 th1 tsu2 th2 tc tr, tf tw tsu th tD tDH Min 1000 450 60 20 195 10 1000 450 60 20 5 Typ Max 25 25 360 ns Unit ns
31
S6A0072
16COM/40SEG DOT MATRIX LCD CONTROLLER & DRIVER
RS
VIH1 VIL1 tsu1 VIL1 tw
th1 VIL1 th1 tf VIH1 VIL1 tsu2 Valid Data tc
R/W
E tr DB0 - DB7
VIH1 VIL1 VIH1 VIL1
VIL1 th2 VIH1 VIL1
Figure 3. Write Mode Timing Diagram
RS
VIH1 VIL1 tsu VIH1 tw
th VIH1 th tf VIH1 VIL1 tD VOH1 VOL1 Valid Data tc tDH VOH1 VOL1
R/W
E tr DB0 - DB7
VIH1 VIL1
VIL1
Figure 4. Read Mode Timing Diagram
32

▲Up To Search▲

Price & Availability of S6A0072

	To Download S6A0072 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .